1. Field of the Invention
The present invention relates to libraries for determining integrated circuit performance and in particular to generating libraries with efficient device mismatch characterization.
2. Discussion of the Related Art
Within-cell variation, or device (e.g. transistor) mismatch variation, refers to process variations that are applied to each individual device within a cell (e.g. standard or macro). Gate level statistical timing tools cannot handle device mismatch variation with full accuracy that requires each device to vary independently. Specifically, the characterization flow becomes very complicated because multiple variation parameters are required per device, thereby making the size of library data unmanageable and commercially unviable.
For better characterization, one current modeling technique treats all device mismatch variations as fully correlated within a cell, but not correlated across cells. The transistor mismatch variations are known to be random (i.e. not correlated) within each cell as well as across different cells. As a result, the transistor-level behavior can be modeled at the cell level to reduce the modeling complexity although introducing some inaccuracy and pessimism (i.e. uncertainty of accuracy) at the cell level. The cancellation effect across cells can mitigate the deviation of this model from the true mismatch model in which cancellation takes place both within-cell and across-cell. As can be expected, this transistor-mismatch solution is most accurate when few transistors are included in the cell arc. Experimental data shows good accuracy for timing paths with 10 cells or more. However, the pessimism is non-trivial in short paths especially with large cells that have many transistors per cell arc.
Therefore, what is needed is an accurate model for random within-cell effects (i.e. effects that occur independently of one another), thereby allowing the generation of variation-aware libraries usable during statistical static timing analysis (SSTA).